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[URGENT] - SOC DFT Design Engineer

Lot I2, Road D1, Saigon Hi-Tech Park, District 9, Ho Chi Minh City

UpdatingCompany size
Software/ProductJob category
2 yearsExperienced level
10 tháng trướcUpdated

Tech stack


Thông tin công việc

Mô tả

General Job Scope

  • Utilizing industrial standard methodology such as Tessent MemoryBIST, IEEE 1687 (IJTAG), SCAN and etc

  • Pick up fundamental concept in general DFx (Design-for-Debug/Testability) architecture, validation and integration knowledge.

  • Understand OVM and able use system Verilog for RTL design/validation task.

Below describe general team job scope, accurate assignment will depend on Interview conversation:

(DFx micro Architecture Engineer)

  • Drive technical readiness (TR), which mean understand customer requirement and further design relevant DFT/DFD/DFV features. DFT stand for Design for testability (tester able -access to PCH), DFD stand for Design for debug (board able access the PCH) and DFV stand for Design for validation (Intel platform, customer board able to access to PCH)

  • Require to understand all DFx sub IPs, knowledge require during research phase to implement in (PCH DFx) One stop DFx complete solution.

  • Besides DFx sub-IP, also require to familiarize other peripheral protocols such as I/O design protocols (SATA, PCIe, USB and etc), which also contain DFx features to be interact.

  • Enhancement on DFx features always as default expectation.

  • Always find opportunity to proliferate DFx design methodology into wide range of product streamline, such as client, Server, mobile and Desktop).

  • Good communication skill, a lot discussion happen across function group (Tester group, platform team, customer team and etc) before execution start. This is to ensure all the features requirement documented and implement in the chip.

(DFx RTL Integration and Design Engineer )

  • Require RTL coding, pick up different RTL tool-based solution. Integrate all other DFx sub-IPs into one stop DFx complete RTL solution (a.k.a DFx IP). Next insert this One Stop DFx complete logic (a.k.a DFx IP) into Main PCH chip. Along process will require signal/clock connection, timing convergence and etc.

  • Responsible to patch RTL logic for flawless area along execution phase. Ensure zero RTL design errors (bug free) as ultimate goal for DFx features.

  • Insert MemoryBIST logics to PCH, as part of the DFT features to enable High Volume Manufacturing (HVM) Memory screening through tests (Post Silicon team).

  • Require good communication skill due to collaborate with geo-diverse teams (full chip, structural design team, other IPs team) in analyzing, debugging and identifying the root cause of issues that arise.

  • Have great opportunity be the RTL logic design lead engineer.

(DFx RTL Verification Engineer )

  • Understand DFD, DFT or DFV features through spec reading, release test plan and develop relevant test script. Ensure all the RTL Design being validated well to eliminate design flawless to customer.

  • Execute Tests script (DFx Tests) with time guide, debug issues and implement fix. Report out test result timely and perform necessary test enhancement steps.

  • Drive test review with counterparts such as Pre-silicon full chip team, IP team, post silicon tester team, board team and etc. Thus require collaborate closely with other function group for test debug, analysis and root cause.

  • In additional, collaborate closely with Post silicon PDE team to enable HVM (high volume manufacturing) testing capability

  • Familiar DFx test Island (Test environment) for validation efficiency, enhancement purpose.

Yêu cầu

Candidate must possess a Bachelor/Masters of Engineering or Science degree in Electronic, Electrical or Computer Engineering.

Additional qualifications include:

  • Familiar with UNIX, and well-versed in Verilog or C Programming.

  • Familiar with Pre-silicon flow, experience in either pre-silicon RTL design or pre-silicon validation task previously.

  • Obtain RTL integration or OVM/UVM validation methodologies gain extra marks.

  • Great communicate skill and no issues in stakeholder management especially with cross-site partners.

  • At least 2 years of working experience.

Thông tin khác

  • Competitive Compensation & Benefit (13th month salary, attractive bonuses,..)

  • Premium Health Care Package for you and your family

  • Attractive Training Programs & Exciting team activities

Nơi làm việc

  • Lot I2, Road D1, Saigon Hi-Tech Park, District 9, Ho Chi Minh City
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